Self-aligned wrapped-around structure
US9478624B2 · kind B2 · utility
23Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate structure extending completely around the first semiconductor structure in a plan view. An outermost perimeter of the gate structure comprises a first protruding arcuate section interposed between linear sections, the first protruding arcuate section aligned with the first semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.