Vertical-gate-all-around devices and method of fabrication thereof
US9478631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.