Resistive switching random access memory with asymmetric source and drain
US9478638B2 · kind B2 · utility
5Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Oct 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.