Synchroniser flip-flop
US9479147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Nov 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.