Trace-based instruction execution processing
US9483264B2 · kind B2 · utility
1Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Aug 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for executing instructions in a thread processing environment includes determining a multiple requirements that must be satisfied and resources that must be available for executing multiple instructions. The multiple instructions are encapsulated into a schedulable structure. A header is configured for the schedulable structure with information including the determined multiple requirements and resources. The schedulable structure is schedule for executing each of the multiple instructions using the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.