Compressed indirect prediction caches
US9483271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2013 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Dec 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/322
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein is a compressed cache design to predict indirect branches in a microprocessor based on the characteristics of the addresses of the branch instructions. In one aspect, a method for predicting a branch target T in a microprocessor includes the following steps. A compressed count cache table (CTABLE) of branch targets indexed using a function combining a branch address and a branch history vector for each of the targets is maintained, wherein entries in the CTABLE contain only low-order bits of each of the targets in combination with an index bit(s) I. A given one of the entries is obtained related to a given one of the branch targets and it is determined from the index bits I whether A) high-order bits of the target are equal to the branch address, or B) the high-order bits of the target are contained in an auxiliary cache table (HTABLE).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.