Patent · US Active

Peripheral component interconnect express (PCIE) pseudo-virtual channels and non-blocking writes

US9483424B1 · kind B1 · utility

2Cited by

4References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Charles Ray Johns · Austin, US
Eric N. Lais · Tillson, US
Jeffrey A. Stuecheli · Austin, US

Key dates

Filing date	Dec 4, 2015
Grant date	Nov 1, 2016
Priority date	—
Expiry date	Dec 4, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure use non-blocking writes (NBWs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using NBWs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may indicate that a TLP includes an NBW. Based on the indication, the root complex may send the NBWs on a dedicated NBW channel such that the NBW is not blocked by normal memory writes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.