Dicing in wafer level package
US9484227B1 · kind B1 · utility
12Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes placing a first device die and a second device die over a carrier, with a scribe line between the first device die and the second device die. The first device die and the second device die are encapsulated with an encapsulating material, which has a portion in the scribe line. The method further includes forming a dielectric layer over the encapsulating material, performing a first die-saw to form a first trench in the scribe line, performing a second die-saw to form a second trench in the scribe line, and performing a third die-saw on the scribe line to separate the first device die from the second device die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.