Device and method for bias control of class A power RF amplifier
US9484862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.