Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
US9489314B2 · kind B2 · utility
4Cited by
0References
7Claims
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Key dates
| Filing date | Oct 24, 2013 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 11, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.