Time division multiplexed multiport memory
US9490006B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.