Method for structuring a layered structure from two semiconductor layers, and micromechanical component
US9490137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 6, 2035 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.