Overlay marks and semiconductor process using the overlay marks
US9490217B1 · kind B1 · utility
9Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Apr 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.