Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width
US9490323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.