Fabrication methodology for optoelectronic integrated circuits
US9490336B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit includes depositing a multilayer metal stack on at least one contact layer of semiconductor material. The multilayer metal stack includes a bottom interface layer formed by a combination of indium and at least one high temperature metal on the at least one contact layer of semiconductor material, at least one barrier layer formed on the bottom interface layer, and a layer formed from at least one high temperature metal on the at least one barrier layer. The metal stack is heated such that indium of the bottom interface layer forms a low resistance interface to contact layer. The at least one barrier layer functions as a barrier to diffusion of indium from the bottom interface layer. Subsequent to the heating, the resultant multilayer metal stack can be patterned to form at least one electrode for a given device of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.