Programmable synchronous clock divider
US9490777B2 · kind B2 · utility
1Cited by
14References
20Claims
0Family size
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Key dates
| Filing date | Feb 10, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.