Glitch-free clock switching circuit using Muller C-elements
US9490789B1 · kind B1 · utility
4Cited by
18References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 27, 2016 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Apr 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller C-elements are connected to the clock and selection lines and first and second logic gates. First and second delay cells are connected to the clock lines and the second and fourth Muller C-elements. A first AND gate is connected to the first clock line, the first Muller C-element, and the first delay cell. A second AND gate is connected to the second delay cell, the third Muller C-element, and the second clock line, and an OR gate is connected to the first and second AND gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.