Phase-locked loop with frequency bounding circuit
US9490824B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2016 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jan 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than a first threshold value, which is greater than a maximum normal operational frequency of the PLL, the frequency bounding circuit forces a charge pump to discharge a loop filter until the oscillating signal frequency is less than a second threshold value that is within the normal operational frequency range of the PLL. When the frequency of the oscillating signal is less than a third threshold value, which is less than a minimum normal operational frequency of the PLL, the frequency bounding circuit forces the charge pump to charge the loop filter until the oscillating signal frequency is greater than a fourth threshold value that is within the normal operational frequency range of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.