Methods for balancing write operations of SLC blocks in different memory areas and apparatus implementing the same
US9495101B2 · kind B2 · utility
7Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.