Two level re-order buffer
US9495159B2 · kind B2 · utility
0Cited by
7References
30Claims
0Family size
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Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.