Mark Dechene
8Patents
1h-index
22Co-inventors
43Inventor score
Filing activity: Sep 27, 2013 → Mar 27, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10860319B2 | Apparatus and method for an early page predictor for a memory paging subsystem | Physics | 1 | Active |
| US10761844B2 | Systems and methods to predict load data values | Physics | 1 | Active |
| US10853078B2 | Method and apparatus for supporting speculative memory optimizations | Emerging Cross-Sectional Technologies | 0 | Active |
| US10379864B2 | Processor prefetch throttling based on short streams | Physics | 0 | Active |
| US10228956B2 | Supporting binary translation alias detection in an out-of-order processor | Physics | 0 | Active |
| US9495159B2 | Two level re-order buffer | Physics | 0 | Active |
| US10956160B2 | Method and apparatus for a multi-level reservation station with instruction recirculation | Physics | 0 | Active |
| US9652236B2 | Instruction and logic for non-blocking register reclamation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.