Systems and methods for reducing memory failures
US9495261B2 · kind B2 · utility
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3References
29Claims
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Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.