Large cluster persistence during placement optimization of integrated circuit designs
US9495501B1 · kind B1 · utility
4Cited by
26References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2016 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.