Inventor · Lagrangeville, NY, US

Shyam Ramji

44Patents
7h-index
59Co-inventors
68Inventor score

Filing activity: Jan 27, 2004 → Feb 10, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7549137B2 Latch placement for high performance and low power circuits Physics 37 Active
US8954912B2 Structured placement of latches/flip-flops to minimize clock power in high-performance designs Physics 16 Active
US7076755B2 Method for successive placement based refinement of a generalized cost function Physics 15 Expired
US7934188B2 Legalization of VLSI circuit placement with blockages using hierarchical row slicing Physics 13 Active
US8010926B2 Clock power minimization with regular physical placement of clock repeater components Physics 11 Active
US7089521B2 Method for legalizing the placement of cells in an integrated circuit layout Physics 11 Expired
US8234615B2 Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout Physics 9 Active
US8782584B2 Post-placement cell shifting Physics 7 Active
US8954915B2 Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit Physics 5 Active
US9418188B1 Optimizing placement of circuit resources using a globally accessible placement memory Physics 4 Active
US8495534B2 Post-placement cell shifting Physics 4 Active
US8595675B1 Local objective optimization in global placement of an integrated circuit design Physics 4 Active
US9495501B1 Large cluster persistence during placement optimization of integrated circuit designs Physics 4 Active
US10558775B2 Memory element graph-based placement in integrated circuit design Physics 4 Active
US8347257B2 Detailed routability by cell placement Physics 4 Active
US10803224B2 Propagating constants of structured soft blocks while preserving the relative placement structure Physics 4 Active
US9436791B1 Optimizing placement of circuit resources using a globally accessible placement memory Physics 3 Active
US9053285B2 Thermally aware pin assignment and device placement Physics 3 Active
US10157255B2 Hierarchically aware interior pinning for large synthesis blocks Physics 2 Active
US9910952B2 Hierarchically aware interior pinning for large synthesis blocks Physics 2 Active
US9858377B2 Constraint-driven pin optimization for hierarchical design convergence Physics 2 Active
US8276105B2 Automatic positioning of gate array circuits in an integrated circuit design Physics 1 Active
US10635773B1 Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement Physics 1 Active
US9703914B2 Optimizing placement of circuit resources using a globally accessible placement memory Physics 1 Active
US10762271B2 Model-based refinement of the placement process in integrated circuit generation Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.