Nonvolatile memory interface for metadata shadowing
US9496018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.