Automatic latch-up prevention in SRAM

US9496024B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Srinivasa Raghavan Sridhara · Plano, US
• Sanjeev Kumar Suman · Bengaluru, IN
• Premkumar Seetharaman · Bengaluru, IN
• Keshav Bhaktavatson Chintamani · Bengaluru, IN
• Atul Ramakant Lele · Kanchinakote, IN
• Raviprakash Suryanarayana Rao · Allen, US
• Parvinder Kumar Rana · Bengaluru, IN
• Ajith Harihara Subramonia · Bengaluru, IN
• Vipul Kumar Singhal · Kanchinakote, IN
• Malav Shrikant Shah · Bengaluru, IN
• Bharath Kumar Poluri · Bengaluru, IN

Key dates

• Filing date: Dec 18, 2015
• Grant date: Nov 15, 2016
• Expiry date: Dec 18, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/413
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.