Dynamically optimizing flash data retention or endurance based on data write frequency
US9496043B1 · kind B1 · utility
21Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data storage system including a non-volatile memory array, a controller determines a write frequency of a logical address mapped to a physical subset of the non-volatile memory array. Based on the determined write frequency of the logical address, the controller dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the block and data retention time of the physical subset of the non-volatile memory array. The at least one operating parameter includes one or more of a set including a pulse budget, a verify voltage and a verify threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.