Memory cell and memory
US9496047B2 · kind B2 · utility
2Cited by
51References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2013 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.