Dummy gate placement methodology to enhance integrated circuit performance
US9496142B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Dec 19, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.