Inventor · Plano, TX, US

Younsung Choi

13Patents

1h-index

8Co-inventors

43Inventor score

Filing activity: Sep 23, 2010 → Jul 17, 2020

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9812452B2	Method to form silicide and contact at embedded epitaxial facet	Electricity	3	Active
US10026837B2	Embedded SiGe process for multi-threshold PMOS transistors	Electricity	1	Active
US9735159B2	Optimized layout for relaxed and strained liner in single stress liner technology	Electricity	1	Active
US10734290B2	Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow	Electricity	0	Active
US8438526B2	Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions	Physics	0	Active
US10559469B2	Dual pocket approach in PFETs with embedded SI-GE source/drain	Electricity	0	Active
US11251093B2	Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow	Electricity	0	Active
US10134643B2	Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow	Electricity	0	Active
US10008499B2	Method to form silicide and contact at embedded epitaxial facet	Electricity	0	Active
US9496142B2	Dummy gate placement methodology to enhance integrated circuit performance	Physics	0	Active
US9583488B2	Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow	Electricity	0	Active
US9947765B2	Dummy gate placement methodology to enhance integrated circuit performance	Physics	0	Active
US9508601B2	Method to form silicide and contact at embedded epitaxial facet	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.