Patent · US Active

Method for forming interconnection structures

US9496172B2 · kind B2 · utility

2Cited by
1References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 27, 2012
Grant dateNov 15, 2016
Priority date
Expiry dateNov 27, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The present invention provides a method for forming interconnection structures, including the following steps: providing a semiconductor wafer with a dielectric layer; forming a first recessed area for forming the interconnection structures and a non-recessed area on the dielectric layer; forming a second recessed area for forming dummy structures on the dielectric layer; depositing a barrier layer to cover the first and second recessed areas and the non-recessed area; depositing a metal layer to fill the first and second recessed areas and cover the non-recessed area; removing the metal layer on the non-recessed area to expose the barrier layer; and removing the barrier layer on the non-recessed area to expose the dielectric layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.