Stacked semiconductor devices and methods of forming same
US9496189B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.