Method and apparatus of forming a via
US9496217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.