Method for forming fuse pad and bond pad of integrated circuit
US9496221B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2012 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.