Low power semiconductor transistor structure and method of fabrication thereof

US9496261B2 · kind B2 · utility

Assignee

• Mie Fujitsu Semiconductor Limited · JP

Inventors

• Lucian Shifren · San Jose, US
• Pushkar Ranade · Los Gatos, US
• Scott E. Thompson · Gainesville, US
• Sachrin R. Sonkusale · Los Gatos, US
• Weimin Zhang · San Jose, US

Key dates

• Filing date: Aug 19, 2013
• Grant date: Nov 15, 2016
• Expiry date: Jun 7, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.