Method for manufacturing semiconductor device
US9496267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | May 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one device, a first space partitioned by first and second line patters is filled with a multilayer film that is composed of a first silicon film having a high impurity concentration relative to a standard plug impurity concentration and a second silicon film having a low impurity concentration relative to the standard plug impurity concentration, and is divided by forming a groove using a mask film on the side wall of the second line pattern. As a result, expansion of a seam, which is formed only on the second silicon film having a low impurity concentration, is suppressed. After that, an isolation insulating film is embedded in the groove and impurity diffusion is carried out by a heat treatment, so that divided plugs as a whole are made to have the standard plug impurity concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.