FinFET isolation structure and method for fabricating the same
US9496363B1 · kind B1 · utility
13Cited by
0References
20Claims
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Key dates
| Filing date | Oct 14, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/687
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a portion of the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.