Non-volatile memory and fabricating method thereof
US9496418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | May 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.