Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof
US9496876B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17748
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of logic tiles, wherein each logic tile is configurable to connect with at least one adjacent logic tile; a first logic tile includes: (i) an input clock path which is associated with an edge and to receive a tile input clock signal, (ii) a plurality of output clock paths, each output clock path is associated with an edge of the tile and includes at least one u-turn circuit to: (a) receive a tile clock signal having a predetermined skew relative to the tile input clock signal and (b) output a tile clock signal having a predetermined skew relative to a tile output clock signal, (iii) a tile clock generation path which includes a plurality of the u-turn circuits to generate a tile clock based on the tile clock signals, and (iv) programmable logic circuitry to perform operations using the tile clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.