Asynchronous SAR ADC with binary scaled redundancy
US9496888B1 · kind B1 · utility
4Cited by
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24Claims
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Key dates
| Filing date | Dec 12, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.