Memory controller for heterogeneous computer
US9501227B2 · kind B2 · utility
3Cited by
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14Claims
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Key dates
| Filing date | Aug 21, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.