Patent · US Active

Integrated circuit design changes using through-silicon vias

US9501603B2 · kind B2 · utility

37Cited by

2References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
Joachim Keinert · Altdorf, DE
Sridhar H. Rangarajan · Savanuru, IN
Haoxing Ren · Austin, US
Sourav Saha · Sherghati, IN

Key dates

Filing date	Sep 5, 2014
Grant date	Nov 22, 2016
Priority date	—
Expiry date	Oct 7, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.