Integration method for a vertical nanowire transistor
US9502310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Mar 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.