Semiconductor package, fabrication method therefor, and package-on package
US9502391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2013 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | May 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.