Nonvolatile memory device having a gate coupled to resistors
US9502468B2 · kind B2 · utility
1Cited by
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14Claims
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Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Aug 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.