Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode
US9502543B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a memory device are described. Generally, the method begins with forming a tunnel dielectric layer over a channel region formed from a silicon containing layer over a surface of a substrate. A first oxygen-rich nitride layer of a multi-layer charge-trapping region is formed on a surface of the tunnel dielectric layer, and a second oxygen-lean nitride layer formed over the first nitride layer. A blocking dielectric layer is formed over a surface of the second layer of the multi-layer charge-trapping region, and a high work function gate electrode upon over the blocking dielectric layer. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.