Resistive random-access memory (RRAM) with a low-K porous layer

US9502647B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Ting-Chang Chang · Hsinchu, TW
• Kuan-Chang Chang
• Tsung-Ming Tsai
• Chih-Hung Pan · Taichung, TW
• Ying-Lang Wang · Zhuolan Township, TW
• Kei-Wei Chen · Tainan, TW
• Shih-Chieh Chang · Taipei, TW
• Te-Ming Kung · Hsinchu, TW

Key dates

• Filing date: May 28, 2014
• Grant date: Nov 22, 2016
• Expiry date: May 28, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.