Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory
US9503091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2013 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxid…
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