Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same
US9503092B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2016 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Feb 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile includes a plurality of (i) computing elements and (ii) switch matrices. The plurality of switch matrices are arranged in stages including (i) a first stage, configured in a hierarchical network (for example, a radix-4 network), wherein, each switch matrix of the first stage is connected to at least one associated computing element, (ii) a second stage configured in a hierarchical network (for example, a radix-2 or radix-3 network) and coupled to switches of the first stage, and (iii) a third stage configured in a mesh network and coupled to switches of the first and/or second stages. In one embodiment, the third stage of switch matrices is located between the first stage and second stage of switch matrices; in another embodiment, the third stage is the highest stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.