Cache as point of coherence in multiprocessor system
US9507647B2 · kind B2 · utility
21Cited by
1References
25Claims
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Key dates
| Filing date | Jan 18, 2011 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.